JS28F512M29EWLB TR

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features Parallel NOR Flash Embedded Memory JS28F256M29EWxx, PC28F256M29EWxx, RC28F256M29EWxx JS28F512M29EWxx, PC28F512M29EWxx, RC28F512M29EWxx JS28F00AM29EWxx, PC28F00AM29EWxx, RC28F00AM29EWxx PC28F00BM29EWxx, RC28F00BM29EWxx Features • VPP/WP# pin protection – Protects first or last block regardless of block protection settings • Software protection – Volatile protection – Nonvolatile protection – Password protection – Password access • Extended memory block – 128-word (256-byte) block for permanent, secure identification – Programmed or locked at the factory or by the customer • Low power consumption: Standby mode • JESD47H-compliant – 100,000 minimum ERASE cycles per block – Data retention: 20 years (TYP) • 65nm multilevel cell (MLC) process technology • Fortified BGA and TSOP packages • Green packages available – RoHS-compliant – Halogen-free • Operating temperature – Ambient: –40°C to +85°C • 2Gb = stacked device (two 1Gb die) • Supply voltage – VCC = 2.7–3.6V (program, erase, read) – VCCQ = 1.65–3.6V (I/O buffers) • Asynchronous random/page read – Page size: 16 words or 32 bytes – Page access: 25ns – Random access: 100ns (Fortified BGA); 110ns (TSOP) • Buffer program: 512-word program buffer • Program time – 0.88µs per byte (1.14 MB/s) TYP when using full 512-word buffer size in buffer program • Memory organization – Uniform blocks: 128-Kbytes or 64-Kwords each • Program/erase controller – Embedded byte/word program algorithms • Program/erase suspend and resume capability – Read from any block during a PROGRAM SUSPEND operation – Read or program another block during an ERASE SUSPEND operation • BLANK CHECK operation to verify an erased block • Unlock bypass, block erase, chip erase, and write to buffer capability – Fast buffered/batch programming – Fast block/chip erase PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features Part Numbering Information Available with extended memory block prelocked by Micron. Devices are shipped from the factory with memory content bits erased to 1. For available options, such as packages or high/low protection, or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products. Contact the factory for devices not found. Table 1: Part Number Information Part Number Category Category Details Package Notes JS = 56-pin TSOP, 14mm x 20mm, lead-free, halogen-free, RoHS-compliant PC = 64-ball Fortified BGA, 11mm x 13mm, lead-free, halogen-free, RoHS-compliant RC = 64-ball Fortified BGA, 11mm x 13mm, leaded Product designator 28F = NOR parallel interface Density 256 = 256Mb 512 = 512Mb 00A = 1Gb 00B = 2Gb Device type M29EW = Embedded Flash memory (3V core, page, uniform block) Device function H = Highest block protected by VPP/WP# 1 L = Lowest block protected by VPP/WP# Features Note: A/B/D/E or an asterisk (*) = Combination of features, including packing media, special features, and specific customer request information 1. For 2Gb device, H also indicates protection of the lowest block by VPP/WP#. Table 2: Standard Part Numbers by Density, Medium, and Package Package Density Medium JS PC RC 256Mb Tray JS28F256M29EWHA PC28F256M29EWHA RC28F256M29EWHA JS28F256M29EWLA PC28F256M29EWLA RC28F256M29EWLA Tape and Reel JS28F256M29EWHB PC28F256M29EWHB RC28F256M29EWHB JS28F256M29EWLB PC28F256M29EWLB – Tray JS28F512M29EWHA PC28F512M29EWHD RC28F512M29EWHA JS28F512M29EWLA PC28F512M29EWLA RC28F512M29EWLA Tape and Reel JS28F512M29EWHB PC28F512M29EWHB RC28F512M29EWHB JS28F512M29EWLB PC28F512M29EWLB – Tray JS28F00AM29EWHA PC28F00AM29EWHA RC28F00AM29EWHA JS28F00AM29EWLA PC28F00AM29EWLA RC28F00AM29EWLA Tape and Reel JS28F00AM29EWHB PC28F00AM29EWHB RC28F00AM29EWHB Tray – PC28F00BM29EWHA RC28F00BM29EWHA 512Mb 1Gb 2Gb Note: 1. For security features and part numbers, contact your local Micron sales representative. PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features Table 3: Part Numbers with Security Features by Density, Medium, and Package Package Density Medium JS PC RC 256Mb Tray – PC28F256M29EWHD – – PC28F256M29EWLD – 512Mb 1Gb Tape and Reel – – – Tray – PC28F512M29EWHA – – PC28F512M29EWLE – Tape and Reel – PC28F512M29EWHE – Tray – PC28F00AM29EWHD – PC28F00AM29EWLE Tape and Reel Note: – – – 1. This data sheet covers only standard parts. For security parts, contact your local Micron sales representative. PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features Contents General Description ......................................................................................................................................... 8 Device Configurability .................................................................................................................................. 9 Signal Assignments ......................................................................................................................................... 10 Signal Descriptions ......................................................................................................................................... 12 Memory Organization .................................................................................................................................... 13 Memory Configuration ............................................................................................................................... 13 Memory Map – 256Mb–2Gb Density ........................................................................................................... 13 Bus Operations ............................................................................................................................................... 14 Read .......................................................................................................................................................... 14 Write .......................................................................................................................................................... 14 Standby ..................................................................................................................................................... 14 Output Disable ........................................................................................................................................... 15 Reset .......................................................................................................................................................... 15 Registers ........................................................................................................................................................ 16 Status Register ............................................................................................................................................ 16 Lock Register .............................................................................................................................................. 21 Standard Command Definitions – Address-Data Cycles .................................................................................... 24 READ and AUTO SELECT Operations .............................................................................................................. 26 READ/RESET Command ............................................................................................................................ 26 READ CFI Command .................................................................................................................................. 26 AUTO SELECT Command ........................................................................................................................... 26 Bypass Operations .......................................................................................................................................... 28 UNLOCK BYPASS Command ...................................................................................................................... 28 UNLOCK BYPASS RESET Command ............................................................................................................ 28 Program Operations ....................................................................................................................................... 29 PROGRAM Command ................................................................................................................................ 29 UNLOCK BYPASS PROGRAM Command ..................................................................................................... 29 WRITE TO BUFFER PROGRAM Command .................................................................................................. 29 UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 31 WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 32 BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 32 PROGRAM SUSPEND Command ................................................................................................................ 32 PROGRAM RESUME Command .................................................................................................................. 33 Erase Operations ............................................................................................................................................ 33 CHIP ERASE Command .............................................................................................................................. 33 UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 33 BLOCK ERASE Command ........................................................................................................................... 34 UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 34 ERASE SUSPEND Command ....................................................................................................................... 35 ERASE RESUME Command ........................................................................................................................ 35 BLANK CHECK Operation .............................................................................................................................. 35 BLANK CHECK Commands ........................................................................................................................ 35 Block Protection Command Definitions – Address-Data Cycles ........................................................................ 37 Protection Operations .................................................................................................................................... 40 LOCK REGISTER Commands ...................................................................................................................... 40 PASSWORD PROTECTION Commands ....................................................................................................... 40 NONVOLATILE PROTECTION Commands .................................................................................................. 40 NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 43 VOLATILE PROTECTION Commands .......................................................................................................... 43 EXTENDED MEMORY BLOCK Commands .................................................................................................. 43 PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features EXIT PROTECTION Command .................................................................................................................... Device Protection ........................................................................................................................................... Hardware Protection .................................................................................................................................. Software Protection .................................................................................................................................... Volatile Protection Mode ............................................................................................................................. Nonvolatile Protection Mode ...................................................................................................................... Password Protection Mode .......................................................................................................................... Password Access ......................................................................................................................................... Common Flash Interface ................................................................................................................................ Power-Up and Reset Characteristics ................................................................................................................ Absolute Ratings and Operating Conditions ..................................................................................................... DC Characteristics .......................................................................................................................................... Read AC Characteristics .................................................................................................................................. Write AC Characteristics ................................................................................................................................. Accelerated Program, Data Polling/Toggle AC Characteristics ........................................................................... Program/Erase Characteristics ........................................................................................................................ Package Dimensions ....................................................................................................................................... Additional Resources ...................................................................................................................................... Revision History ............................................................................................................................................. Rev. B – 08/12 ............................................................................................................................................. Rev. A – 04/12 ............................................................................................................................................. PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 5 44 45 45 45 46 46 47 47 49 53 55 57 59 62 69 71 72 74 75 75 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 8 Figure 2: 2Gb Configuration ............................................................................................................................ 9 Figure 3: 56-Pin TSOP (Top View) .................................................................................................................. 10 Figure 4: 64-Ball Fortified BGA ....................................................................................................................... 11 Figure 5: Data Polling Flowchart .................................................................................................................... 18 Figure 6: Toggle Bit Flowchart ........................................................................................................................ 19 Figure 7: Status Register Polling Flowchart ..................................................................................................... 20 Figure 8: Lock Register Program Flowchart ..................................................................................................... 22 Figure 9: Boundary Condition of Program Buffer Size ..................................................................................... 30 Figure 10: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 31 Figure 11: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 42 Figure 12: Software Protection Scheme .......................................................................................................... 47 Figure 13: Power-Up Timing .......................................................................................................................... 53 Figure 14: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 54 Figure 15: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 54 Figure 16: AC Measurement Load Circuit ....................................................................................................... 56 Figure 17: AC Measurement I/O Waveform ..................................................................................................... 56 Figure 18: Random Read AC Timing (8-Bit Mode) ........................................................................................... 60 Figure 19: Random Read AC Timing (16-Bit Mode) ......................................................................................... 60 Figure 20: BYTE# Transition Read AC Timing .................................................................................................. 61 Figure 21: Page Read AC Timing (16-Bit Mode) ............................................................................................... 61 Figure 22: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 63 Figure 23: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 64 Figure 24: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 66 Figure 25: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 67 Figure 26: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 68 Figure 27: Accelerated Program AC Timing ..................................................................................................... 69 Figure 28: Data Polling AC Timing .................................................................................................................. 69 Figure 29: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 70 Figure 30: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 72 Figure 31: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 73 PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Features List of Tables Table 1: Part Number Information ................................................................................................................... 2 Table 2: Standard Part Numbers by Density, Medium, and Package ................................................................... 2 Table 3: Part Numbers with Security Features by Density, Medium, and Package ................................................ 3 Table 4: Signal Descriptions ........................................................................................................................... 12 Table 5: Blocks[2047:0] .................................................................................................................................. 13 Table 6: Bus Operations ................................................................................................................................. 14 Table 7: Status Register Bit Definitions ........................................................................................................... 16 Table 8: Operations and Corresponding Bit Settings ........................................................................................ 17 Table 9: Lock Register Bit Definitions ............................................................................................................. 21 Table 10: Block Protection Status ................................................................................................................... 21 Table 11: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ........................................... 24 Table 12: Read Electronic Signature ............................................................................................................... 27 Table 13: Block Protection ............................................................................................................................. 27 Table 14: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 37 Table 15: Extended Memory Block Address and Data ...................................................................................... 43 Table 16: V PP/WP# Functions ......................................................................................................................... 45 Table 17: Query Structure Overview ............................................................................................................... 49 Table 18: CFI Query Identification String ........................................................................................................ 49 Table 19: CFI Query System Interface Information .......................................................................................... 50 Table 20: Device Geometry Definition ............................................................................................................ 50 Table 21: Primary Algorithm-Specific Extended Query Table ........................................................................... 51 Table 22: Power-Up Specifications ................................................................................................................. 53 Table 23: Reset AC Specifications ................................................................................................................... 54 Table 24: Absolute Maximum/Minimum Ratings ............................................................................................ 55 Table 25: Operating Conditions ...................................................................................................................... 55 Table 26: Input/Output Capacitance .............................................................................................................. 56 Table 27: DC Current Characteristics .............................................................................................................. 57 Table 28: DC Voltage Characteristics .............................................................................................................. 58 Table 29: Read AC Characteristics .................................................................................................................. 59 Table 30: WE#-Controlled Write AC Characteristics ......................................................................................... 62 Table 31: CE#-Controlled Write AC Characteristics ......................................................................................... 65 Table 32: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 69 Table 33: Program/Erase Characteristics ........................................................................................................ 71 Table 34: Technical Notes .............................................................................................................................. 74 PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash General Description General Description The M29EW is an asynchronous, uniform block, parallel NOR Flash memory device manufactured on 65nm multilevel cell (MLC) technology. READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to most microprocessors, often without additional logic. The M29EW supports asynchronous random read and page read from all blocks of the array. It also features an internal program buffer that improves throughput by programming 512 words via one command sequence. The device contains a 128-word extended memory block which overlaps addresses with array block 0. The user can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification. Figure 1: Logic Diagram VCC VCCQ VPP/WP# 15 A[MAX:0] DQ[14:0] DQ15/A-1 WE# CE# RY/BY# OE# RST# BYTE# VSS PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash General Description Device Configurability Figure 2: 2Gb Configuration VPP / WP# CE# OE# Upper die (1Gb) WE# VCCQ RST# VSS BYTE# Lower die (1Gb) A[26:0] Note: PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN VCC DQ[14:0] DQ15/A-1 RY/BY# 1. A[26] = VIH selects the upper die; A[26] = VIL selects the lower die. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Signal Assignments Signal Assignments Figure 3: 56-Pin TSOP (Top View) A23 A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 VPP/WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 RFU RFU Notes: PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1. 2. 3. 4. A24 A25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 RFU VCCQ A-1 is the least significant address bit in x8 mode. A23 is valid for 256Mb and above; otherwise, it is RFU. A24 is valid for 512Mb and above; otherwise, it is RFU. A25 is valid for 1Gb and above; otherwise, it is RFU. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Signal Assignments Figure 4: 64-Ball Fortified BGA 2 1 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A RFU A3 A7 RY/BY# WE# A9 A13 RFU RFU A13 A9 WE# RY/BY# A7 A3 RFU B B A26 A4 A17 VPP/WP# RST# A8 A12 A22 A22 A12 A8 RST# VPP/WP# A17 A4 A26 C C RFU A2 A18 A6 A21 A10 A14 A23 A23 A14 A10 A21 A18 A6 A2 RFU D D RFU A1 A20 A5 A19 A11 A15 VCCQ VCCQ A15 A11 A19 A20 A5 A1 RFU E E RFU A0 D0 D2 D5 D7 VCCQ CE# D8 D10 D12 RFU OE# D9 D11 RFU VSS D1 D3 A16 VSS VSS A16 D7 D5 D2 D0 A0 RFU D14 BYTE# A24 A24 BYTE# D14 D12 D10 D8 CE# VCCQ VCC D13 D15/A-1 A25 A25 D15/A-1 D13 VCC D11 D9 OE# RFU D4 D6 RFU D6 D4 D3 D1 VSS RFU F F G G H H VSS RFU Fortified BGA Top view – ball side down Notes: PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 1. 2. 3. 4. 5. VSS Fortified BGA Bottom view – ball side up A-1 is the least significant address bit in x8 mode. A23 is valid for 256Mb and above; otherwise, it is RFU. A24 is valid for 512Mb and above; otherwise, it is RFU. A25 is valid for 1Gb and above; otherwise, it is RFU. A26 is valid for 2Gb only; otherwise it is RFU. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for this device family. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 4: Signal Descriptions Name Type Description A[MAX:0] Input Address: Selects the cells in the array to access during READ operations. During WRITE operations, they control the commands sent to the command interface of the program/erase controller. CE# Input Chip enable: Activates the device, enabling READ and WRITE operations to be performed. When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z. OE# Input Output enable: Controls the bus READ operation. WE# Input Write enable: Controls the bus WRITE operation of the command interface. VPP/WP# Input VPP/Write Protect: Provides WRITE PROTECT function and VPPH function. These functions protect the lowest or highest block and enable the device to enter unlock bypass mode, respectively. (Refer to Hardware Protection and Bypass Operations for details.) BYTE# Input Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is LOW, the device is in x8 mode; when HIGH, the device is in x16 mode. RST# Input Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details. DQ[7:0] I/O Data I/O: Outputs the data stored at the selected address during a READ operation. During WRITE operations, they represent the commands sent to the command interface of the internal state machine. DQ[14:8] I/O Data I/O: Outputs the data stored at the selected address during a READ operation when BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE operations, these bits are not used. When reading the status register, these bits should be ignored. DQ15/A-1 I/O Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8 mode). RY/BY# Output Ready busy: Open-drain output that can be used to identify when the device is performing a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. After a hardware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET AC Specifications for more details). The use of an open-drain output enables the RY/BY# pins from several devices to be connected to a single pull-up resistor to VCCQ. A low value will then indicate that one (or more) of the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V VOL. PDF: 09005aef849b4b09 m29ew_256mb_2gb.pdf - Rev. B 8/12 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash Memory Organization Table 4: Signal Descriptions (Continued) Name Type VCC Supply Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations. The command interface is disabled when VCC